1. Technical Field
The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device which is built in a system-on-chip (SOC).
2. Description
Operation of a semiconductor memory device built in a conventional system-on-chip (SOC) includes a pre-charge operation, a write operation, and a read operation. The pre-charge operation pre-charges bit line pairs and sense bit line pairs to a pre-charge voltage level before a write operation and a read operation in response to a pre-charge enable signal. The write operation writes write data to selected memory cells through write bit line pairs and bit line pairs in response to a write enable signal. The read operation reads data stored in the selected memory cells through bit line pairs and sense bit line pairs in response to a read enable signal.
A column selecting circuit of the conventional semiconductor memory device includes a PMOS transistor and an NMOS transistor which are connected to bit lines and inverted bit lines. For the read operation, the PMOS transistors connected between the bit line pairs and the sense bit line pairs are turned on, thereby reading data stored in the selected memory cells through bit line pairs and sense bit line pairs. For the write operation, the NMOS transistors connected between bit line pairs and write bit line pairs as well as the PMOS transistors connected between bit line pairs and sense bit line pairs are turned on, thereby writing write data to selected memory cells through write bit line pairs and bit line pairs.
Therefore, since both PMOS transistors and NMOS transistors including the column selecting circuit are turned on for the write operation, even sense bit line pairs as well as write bit line pairs and bit line pairs operate. Hence, the conventional semiconductor memory device has a problem in that power consumption increases during a write operation.
It is an object of the present invention to provide a semiconductor memory device which can reduce power consumption during a write operation.
In accordance with one aspect of the present invention, a semiconductor memory device includes a plurality of memory cell array blocks including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs, each of the memory cell array blocks including a column selecting circuit having a plurality of first transmission transistors for transmitting data between the selecting bit line pair among the plurality of the bit line pairs and a write bit line pair in response to a plurality of write control signals, and a plurality of second transmission transistors for transmitting data between the selected bit line pair and a sense bit line pair in response to a plurality of read control signals; and a pre-charge and write control circuit for pre-charging and equalizing the sense bit line pair in response to a pre-charge enable signal during a pre-charge operation, generating the plurality of the read control signals in response to a write enable signal and a plurality of column selecting signals during a read operation, and generating the plurality of write control signals in response to a block selecting signal, the write enable signal, the pre-charge enable signal, and the plurality of the column selecting signals during a write operation.
The pre-charge and write control circuit includes a pre-charge and equalizing circuit for pre-charging and equalizing the sense bit line pair in response to the pre-charge enable signal; a write control signal generating circuit for generating a write control signal by combining the block selecting signal, the write enable signal and the pre-charge enable signal; a read control signal generating circuit for generating the plurality of the read control signals by combining the plurality of the column selecting signals and the write enable signal; and a write control signal generating circuit for generating the plurality of the write control signals by combining the plurality of the column selecting signals and the write control signal, wherein all of the plurality of the first and the second transmission transistors are turned off during a pre-charge operation, and the selected first transmission transistors among the plurality of the first and the second transmission transistors are turned on during a write operation.
In accordance with another aspect of the present invention, a semiconductor memory device includes a plurality of memory cell array blocks including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs, each of the memory cell array blocks including a column selecting circuit having a plurality of first transmission transistors for transmitting data between the selecting bit line pair among the plurality of the bit line pairs and a write bit line pair in response to a plurality of write control signals, and a plurality of second transmission transistors for transmitting data between the selected bit line pair and a sense bit line pair in response to a plurality of read control signals; and a pre-charge and write control circuit for equalizing the sense bit line pair in response to a pre-charge enable signal during a pre-charge operation, generating the plurality of the read control signals in response to a write enable signal, the pre-charge enable signal and a plurality of column selecting signals during a read operation, and generating the plurality of write control signals in response to a block selecting signal, the write enable signal, the pre-charge enable signal, and the plurality of the column selecting signals during a write operation.
The pre-charge and write control circuit includes an equalizing circuit for equalizing the sense bit line pair in response to the pre-charge enable signal; a write control signal generating circuit for generating a write control signal by combining the block selecting signal, the write enable signal and the pre-charge enable signal; a read control signal generating circuit for generating the plurality of the read control signals by combining the plurality of the column selecting signals, the write enable signal and the pre-charge enable signal; and a write control signal generating circuit for generating the plurality of the write control signals by combining the plurality of the column selecting signals and the write control signal, wherein the plurality of the second transmission transistors are turned on during a pre-charge operation, and the selected first transmission transistors among the plurality of the first and the second transmission transistors are turned on during a write operation.